FIG. 1 shows a block diagram of an electronic system 100 having a plurality of masters sharing access to a memory device. Referring to FIG. 1, a plurality of masters including a first master 102, a second master 104, and a third master 106 share access to a multi-port memory device 108 which may be a multi-port SDRAM (synchronous dynamic random access memory). One of ordinary skill in the art is familiar with a SDRAM that operates synchronously with a clock signal from a master. In addition, a SDRAM is a command-based memory device with a master indicating a command by setting the logic states of a plurality of control signals.
The SDRAM 108 is deemed multi-port because the SDRAM 108 has a plurality of ports including a first port 112, a second port 114, and a third port 116. Each of the first, second, and third ports 112, 114, and 116 has a respective established signal interface SIF1, SIF2, or SIF3 for communication with a respective controller 122, 124, or 126 of the respective master 102, 104, or 106. Each of the signal interfaces SIF1, SIF2, and SIF3 is used for communication of control signals and data between the respective master 102, 104, or 106 and the SDRAM 108.
In the prior art, an arbitrator 118 coordinates access to the SDRAM 108 among the plurality of masters 102, 104, and 106. Each of the controllers 122, 124, and 126 sends a respective request for access signal REQ1, REQ2, or REQ3 to the arbitrator when desiring access for reading from or writing to the SDRAM 108. The arbitrator then sends a respective acknowledge signal ACK1, ACK2, or ACK3 to each of the controllers 122, 124, and 126.
Generally, one of the masters 102, 104, and 106 is granted access for reading from or writing to the SDRAM 108 at a time by the arbitrator 118. For example, one of the acknowledge signals ACK1, ACK2, and ACK3 is activated for indicating that the corresponding one of the masters 102, 104, and 106 is granted access. Such a prior art arbitration scheme of FIG. 1 disadvantageously requires respective two additional I/O (input/output) pins for the request for access and acknowledge signals at each of the masters 102, 104, and 106 and at each of the ports 112, 114, and 116 of the SDRAM 108.
FIG. 2 shows an electronic system 150 having a plurality of masters 152, 154, and 156 with respective controllers 162, 164, and 166 sharing access to a SDRAM 170 with multiple ports 172, 174, and 176. Each of the masters 152, 154, and 156 has a respective interface SIF1, SIF2, or SIF3 for exchange of control signals and data with a respective port 172, 174, or 176 of the SDRAM 170.
The electronic system 150 of FIG. 2 does not require two additional pins for the request for access and acknowledge signals. Rather, software within each of the masters 152, 154, and 156 arbitrates for access to the SDRAM 170. The masters 152, 154, and 156 communicate such arbitration amongst them-selves via UART (universal asynchronous receiver/transmitter) interfaces 182 and 184.
The prior art arbitration scheme of FIG. 2 disadvantageously requires the Additional UART interfaces 182 and 184 amongst the masters 152, 154, and 156. Also, exchange of request for access and acknowledge information amongst the masters 152, 154, and 156 introduces undesired time delay for signal processing in the electronic system 150. Furthermore, as the number of masters increases, the software complexity in turn increases.
Thus, a more efficient mechanism which also does not require additional I/O pins is desired for arbitrating access to a shared memory device among a plurality of masters.